After the Selloff, ASML Shares Now Undervalued

We also include comments from the third-quarter earnings call.

1) What is Baked Into ASML’s Current Share Price?

Share prices are implying that ASML’s 2030 financial performance is in line with the worst-case scenario stated in the 2022 Investor Day. This means EUR 46.7 billion in 2030 revenue (2030 guidance is EUR 44 billion-60 billion), 56% gross margins (guided range of 56%-60%) and EUR 8.2 billion in R&D plus operating expenses (guided range of EUR 7.6 billion-8.2 billion). This scenario looks too pessimistic to us, meaning the selloff is a buying opportunity.

Key Morningstar Metrics for ASML

• Fair Value Estimate: EUR 850
• Morningstar Rating: ★★★★
• Economic Moat: Wide
• Morningstar Uncertainty Rating: High

2) What Will Revenue Growth Be in the Next Decade?

ASML’s revenue growth will come from higher volumes, higher selling prices and growth in service revenue. It’s a given that lithography intensity is slowing, which is why investors should not expect the same growth from ASML in the future than in the past decade (22% CAGR from 2016-23). Still, we model ASML will grow revenue at a high-single-digit to low-double-digit rate in the next decade coming from more fabs, more systems per fab, higher selling prices and growth in service revenue.

Despite the slowing of Moore’s law, ASML is still managing to shrink chip resolutions that, together with new transistor architectures like gate-all-around, or GAA, and CFET after, will require more lithography intensity. As ASML improves not only the technology, but the productivity of its machines, it can justify charging higher prices to its customers. For instance, if equipment prices jump 20% but productivity jumps 40%, the cost per wafer for the foundry still goes down.

Newer machines like the NXE:3800E, being introduced now, also deliver higher gross margins due to their higher price and cost efficiencies of leveraging several existing EUV, or extreme ultraviolet, product platforms. EUV service is another lever ASML can use to improve gross margins. EUV gross margins are still dilutive to the group as it is a less-mature platform than DUV, or deep ultraviolet, whose service gross margins are higher than the overall group. As happened with DUV two decades ago, ASML is gradually improving its EUV service margins by developing expertise, improving machine uptime and upselling services, software and upgrades. Over its 30-year lifetime, an EUV unit can generate 1.5 times or more of service revenue compared with its equipment revenue, compared to DUV’s 1.3 times.

3) How do Intel’s Problems Affect ASML?

Intel is likely ASML’s third-largest customer, after TSMC and Samsung. Although performance can vary widely by years, we estimate Intel represents between 10%-20% of ASML’s revenue. In early September, Intel announced a capital expenditure cut of 20% and, although we don’t have a full breakdown, we can assume it has affected ASML’s orders. Intel also delayed the start of construction of its Magdeburg fab in Germany, which is EUV intensive (both Low and High NA), by at least until 2025, and we would not be surprised to see more delays given Intel’s challenges.

We believe Intel’s problems are more relevant in the short term and less relevant in the long term. The technological and operational gap between TSMC and its peers Intel and Samsung keeps widening. Should Intel foundries have more delays, or should Intel be unable to deliver on its promises in the coming years, we estimate someone else, likely TSMC, would pick up on the extra chip supply needed.

4) Will TSMC Become an Even Bigger Customer?

Yes. On top of Intel’s specific problems, Samsung issued on Oct. 8 a letter to investors and customers, where it apologizes for failing to meet expectations and where it cites technological competitiveness as one of the key areas to improve. Intel and Samsung’s integrated business model is more inherently difficult than, and disadvantaged to, the manufacturing-only business model of TSMC in our view, as the complexity of designing and manufacturing chips at the same time is enormous.

Some of Intel and Samsung foundry customers might be skeptical to share their chip designs with these firms, as they might fear their designs could be copied if there is not proper separation between design and manufacturing operations. As TSMC is only a manufacturer, it does not have to deal with the complexities of chip design and can focus on maintaining its position as the world’s best fab operator. As TSMC likely gains share from its peers, it should become a larger customer for ASML.

Since early 2020 TSMC has on average represented 33% of ASML’s sales, with huge variations between quarters given the lumpy nature of ASML business. As TSMC becomes an even larger customer it could try to put more pressure on ASML to lower the price of its equipment. Although both companies have refrained from exerting leverage on the other so far, we believe this is an important long-term risk to watch out for. ASML’s best strategy to offset this risk is to continue delivering productivity improvements, which it has successfully done so far. The improved productivity of the NXE:3800E, along with the High-NA EUV EXE:5000, which will have a productivity of 220 wafers per hour by 2025, up from 185, serves as good evidence. TSMC’s strategy to extract more value from the supply chain not only involves pressuring ASML, but also raising prices to customers, as it reportedly did with Nvidia during the summer.

5) ASML’s High-NA EUV: What Is It?

TSMC and Intel have already ordered their first High-NA EUV tools, not yet used in volume manufacturing but only in a R&D environment, and we expect Samsung to follow soon.

A modern chip contains dozens of lithography layers. The deepest layers are the most critical, as this is where most of the computational activity happens, while more superficial layers are less critical. In many cases not all layers require EUV technology, only the deepest ones, and a more mature technology like DUV is good enough, and cheaper, for the more superficial layers.

For advanced chips manufactured at leading nodes, most EUV layers can still be printed using low-NA EUV equipment with double patterning. Double patterning means exposing the wafer twice to the EUV light instead of once. However, as patterns become smaller and the industry moves to new transistor architectures like gate-all-around, the defect rates of using double patterning with low-NA EUV increase, and at some point high-NA EUV becomes cheaper, faster, and provides less defects. According to Digitimes, TSMC will incorporate high-NA EUV into high volume production in 2028, although in our view this schedule can be pushed slightly forward or backward.

Investors often ask how foundries are willing to pay EUR 180 (Low-NA) to EUR 350 (High-NA) million price tags for ASML EUV machines. Semiconductor foundries don’t look at the price of the machine per se, but at the price per wafer produced. Foundries have huge fixed-cost bases, so higher productivity means higher operating leverage and lower costs per unit. Over the past decade, ASML has proved it can deliver not only on the technological side but also on the productivity side. ASML’s new NXE: 3800E (low-NA) is the best example. While previous generations of machines like the NXE:3600D had an output of 160 wafers per hour, NXE:3800E does 220, a 37.5% improvement. This saves costs for foundries, so ASML can justify charging higher prices.

ASML is also delivering on this front for high-NA EUV. The EXE:5000 will improve from 185 wafers per hour to 220 in 2025, a performance at par with the NXE:3800E. ASML knows how important this is for its customers, and we expect the firm will keep focusing on delivering productivity improvements to reduce customers’ cost per wafer. Now that ASML has several EUV product platforms it can improve commonality among them, with machines sharing parts and systems which reduces design complexity, cost, and improves lead times.

6) What is the China Situation for ASML?

Given the news flows in the past two years, we believe it’s more likely that restrictions will go up than down. In our view, the US still has effective power to limit ASML exports. As far as ASML’s machines contain US parts, like its critical light source manufactured in San Diego, Calif., the US has effective power to limit ASML’s exports and put pressure on the Netherlands. Management commented it expects China to fall to around 20% of total revenue in 2025 from 50% in the first nine months of 2024. This normalization of revenue was known by investors as management has already guided about it. ASML’s view is that China is the only country in the world adding semiconductor capacity for more mature applications like automotive or industrial, which are also growing.

In the short term, the impact of China on ASML’s business is relevant. In a 5 year-10-year horizon, China becomes a less important matter, as we expect EUV will represent more than 70% of ASML’s revenue by 2030 (in which China does not participate) and even a higher percentage of profits as EUV has better gross margins, average selling prices and potential for service revenue. We estimate that, by 2030, China will represent 15% or less of ASML’s revenue.

7) Comments on the ASML Q3 Earnings Call

When asked how many EUV systems will be pushed to 2026 given the weaker 2025 demand, management did not give a clear answer. ASML expects some systems will be pushed out to 2026, but there is still uncertainty as it is still early to tell. We expect low-NA EUV deliveries in the mid- to high-60s range in 2026 compared with around 50 in 2025, which is the main contributor to our 13% revenue growth forecast in 2026.

Management also noted that the slower demand for its tools is a combination of both sluggish consumer segments, like PC and smartphones, but also customer-specific issues on technology node advancements. We surmise this last comment mainly refers to Intel and Samsung. If technological struggles persist or worsen, they could take years to solve and cause a potential misalignment of supply and demand, given the multi-year timelines associated with building a new semiconductor fab.